System Level Comparative Performance Analysis of H.264 Encoder by Network-on-Chip Topologies

نویسندگان

  • Suk Ki Lee
  • Jong Kang Park
  • Jong Tae Kim
چکیده

This paper describes comparative analysis results of system performance by network-on-chip topologies on system level. Network-on-chip systems are implemented by typical topologies, mesh topology, crossbar topology, folded torus topology and point-to-point topology on system level. Running the x264/AVC encoding application on each system and analyze performance from simulation results. We can find the fact that performance differences exist when running the benchmark application, by network-on-chip topologies in advance. On each implemented system, there are performance differences ranged from -5.45% to +4.75% based on mesh topology. For analyzing the effect of topologies, we use the CPUs total cycles, which reflect communication latency. Types of topologies affect the number of routers on the paths related to latency and performance. More components of onchip network reinforce such trends. We analyze the reason why each topology has different result. Used approach helps to find optimal topology by changing various on-chip-network topologies on system level

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

High Level Optimized Parallel Specification of a H.264/AVC Video Encoder

H.264/AVC (Advanced Video Codec) is a new video coding standard developed by a joint effort of the ITU-TVCEG and ISO/IEC MPEG. This standard provides higher coding efficiency relative to former standards at the expense of higher computational requirements. Implementing the H.264 video encoder for an embedded Systemon-Chip (SoC) is thus a big challenge. For an efficient implementation, we motiva...

متن کامل

Energy-efficient Fine-grained Many-core Architecture for Video and DSP Applications

Many-core processor architecture has become the most promising computer architecture. However, how to utilize the extra system performance for real applications such as video encoding is still challenging. This dissertation investigates architecture design, physical implementation and performance evaluation of a fine-grained many-core processor for advanced video coding with a focus on intercon...

متن کامل

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

Network-on-Chips (NoCs) are used to connect large numbers of processors in many-core processor architecture because they perform better than less scalable methods such as global shared buses. Among all NoC design parameters, NoC topologies define how nodes are placed and connected and greatly affect the performance, energy efficiency, and circuit area of many-core processor arrays. Due to its s...

متن کامل

Reliability and Performance Evaluation of Fault-aware Routing Methods for Network-on-Chip Architectures (RESEARCH NOTE)

Nowadays, faults and failures are increasing especially in complex systems such as Network-on-Chip (NoC) based Systems-on-a-Chip due to the increasing susceptibility and decreasing feature sizes. On the other hand, fault-tolerant routing algorithms have an evident effect on tolerating permanent faults and improving the reliability of a Network-on-Chip based system. This paper presents reliabili...

متن کامل

Cost-aware Topology Customization of Mesh-based Networks-on-Chip

Nowadays, the growing demand for supporting multiple applications causes to use multiple IPs onto the chip. In fact, finding truly scalable communication architecture will be a critical concern. To this end, the Networks-on-Chip (NoC) paradigm has emerged as a promising solution to on-chip communication challenges within the silicon-based electronics. Many of today’s NoC architectures are based...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:

دوره   شماره 

صفحات  -

تاریخ انتشار 2014